Qwen2.5-VL-32B-Instruct
Support summary
Qwen2.5-VL-32B-Instruct is a checkpoint published by Qwen, built on the Qwen2_5_VLForConditionalGeneration architecture. vLLM 0.28.0, the newest indexed vLLM release, documents support. TensorRT-LLM lists its architecture, but not this exact checkpoint.
vLLM documents support in 20 of 20 indexed releases, from 0.17.0 to 0.28.0.
- Documented hardware
- Intel GPU / XPU
- Configured context
- 128,000 tokens
- License
- apache-2.0
Hardware, quantization and features count only statements about this checkpoint; engine-wide capabilities are listed with each release.
Hugging Face model card
- Publisher
- Qwen
- Task
- image text to text
- License
- apache-2.0
- Library
- transformers
- Architecture
- Qwen2_5_VLForConditionalGeneration
- Weight tensor elements
- 33.5B
- Tensor types
- BF16, F32
- Configured context
- 128,000 tokens
- Languages
- en
- Weight access
- Public
- Repository created
- 2025-03-21
Model notes and sources
Engine support
3 engines
| Engine | Release | Checkpoint support | Evidence scope | Last known supported |
|---|---|---|---|---|
| vLLM | 0.28.0Newest indexed | Checkpoint evidenceSource: vLLM v0.28.0 · docs/models/hardware_supported_models/xpu.mdReviewed | 0.28.0This release | |
Features, dependencies and evidence for vLLM 0.28.0 | ||||
| SGLang | 0.5.19Newest indexed | No matching evidence curated | No supported release indexed | |
Features, dependencies and evidence for SGLang 0.5.19 | ||||
| TensorRT-LLM | 1.2.1Newest indexed | Architecture listed; exact checkpoint unknown | No supported release indexed | |
Features, dependencies and evidence for TensorRT-LLM 1.2.1 | ||||